1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and in particular relates to a method for fabricating a semiconductor device for increasing operation voltage.
2. Description of the Related Art
High voltage MOS transistors are widely used in many electronic devices, such as central processing unit voltage supply devices, power supply manager system devices and AC/DC inverters and the like. Because high voltage MOS transistors are usually operated under high operation voltage, a high electric field may be formed, resulting in a large number of hot electrons near the junction region of the channel and the drain. The hot electrons will excite the electrons near the drain to the conduction band to form an electron-hole pair, thereby affecting covalent electrons near the drain. Most of the electrons ionized by hot electrons may move to the drain to increase drain current (Isub), and a small portion of the ionized electrons may be injected into and trapped by the gate oxide, resulting in changing the threshold voltage of a gate electrode. Additionally, the holes resulting from hot electrons may flow to the substrate to produce a drain current (Isub). Thus, when the operation voltage increase, the number of electron-hole pair increases and results in “carrier multiplication”.
FIG. 1 shows a cross-section view of a traditional high voltage MOS transistor with a lateral diffused drain. As FIG. 1 shows, a high voltage MOS transistor 130 is formed on a semiconductor wafer 110. The semiconductor wafer 110 has a P-type silicon substrate 111 and a P-type epitaxial layer 112 formed on the P-type silicon substrate 111. The high voltage MOS transistor 130 has a P-type well 121, N-type source region 122 formed in the P-type well 121, an N-type drain region 124 formed in the P-type epitaxial layer 112, and a gate electrode 114.
When the drain current mentioned above flows through the P-type silicon substrate 111, the resistance (Rsub) of the P-type silicon substrate 111 may produce an induced voltage (Vb). If the induced voltage is large enough, forward bias may occur between the P-type silicon substrate 111 and the source region 122 to form a parasitic bipolar transistor 140. When the parasitic bipolar transistor 140 is turned on, the current from the drain region 124 flowing to source region 122 is rapidly increased, resulting in electrical breakdown to cause the high voltage MOS transistor 130 to malfunction.
In some high voltage MOS devices, in order to provide a high voltage, “double diffused drain” structures are used in the source and drain. FIG. 2 shows a high voltage MOS transistor with a double diffused drain structure disclosed by U.S. Pat. No. 5,770,880. A substrate 210 has an N-type body 212. A gate 220 on a gate oxide 222 is formed between a source 230 and a drain 240. The source and drain are substantially the same and interchangable, therefore only the drain is described in the flowing. Every drain has a double diffuse region comprising a first heavily doped contact region 214 and a lightly doped region 216. The diffusion regions are formed by implanting P-type ions such as boron into the exposed surface of the substrate after forming an open 219 on the oxide layer and performing an annealing process to make P-type ions diffuse into the substrate 210 to form the doped regions 214 and 216. The contact region 214 is usually limited on the surface of the N-type body 212 and do not extend into the N-type body 212. The second lightly doped region 216 extends into the N-type body 212 and a portion of the second lightly doped region 216 is under the gate electrode 220. A junction region is formed between the doped region 216 and N-type body 212 and the junction region determines the breakdown voltage value of the device. The diffusion doped region 216, having a low doping concentration gradient, may decrease the reverse bias electric field near the body-drain junction region. Specifically, this allows the device to operate under a high voltage before reaching the breakdown voltage. However, fabricating the device mentioned above requires a complicated process and additional masks may be needed, thus increasing costs. Therefore, a new semiconductor device and a fabrication method thereof are needed to improve the breakdown voltage of the device without incurring extra costs.